An exemplary embodiment of the present invention relates to an apparatus for processing a register window overflow and underflow, and more particularly, to an apparatus for processing a register window overflow and underflow which processes a window overflow or a window underflow or both in a Reduced Instruction Set Computer (RISC) processor having a register window structure.
An amount of digital signal processing is indispensable in smart phones and digital multimedia devices which are recently being used a lot. In order to efficiently process a large number of operations, most of devices adopt a processor in an embedded form. Furthermore, there is an increasing demand for the processor of an embedded form because the functions of not only up-to-date high-tech devices, but also lots of household electric appliances being used in daily life become various and complicated.
However, a computational load to be processed is gradually increasing because the complexity of algorithms in applied fields is increasing, and thus a high-performance processor having a very high operating frequency and an RISC structure is mounted on the above-described devices. Accordingly, the use of the high-performance processor is increasing. In general, processors having the RISC structure enable a high operating frequency to be designed because they are characterized in a register-based operation and a simple instruction set.
The RISC processor has a computer structure in which all instructions other than instructions, such as LOAD and STORE for memory access, use registers as operands in order to perform a program at a high speed. In addition, the RISC processor is characterized in that a unified instruction structure, a small number of instruction sets, a high-speed pipeline structure, and a register window.
From among them, a register window is a set of overlapping registers and is configured in a window form. The register window consists of a set of local registers, incoming registers, outgoing registers, and global registers. When a program is executed, one procedure may use a set of registers on one specific window in a register window and has a set of global registers which may be jointly used by all the procedures of the program.
An advantage of this register window structure is that a call to a procedure may be rapidly performed. If a procedure is called when a program is executed, a parameter may be transferred by only changing a window without the need to newly perform memory access because the caller parameter part of a register window now being used and the callee parameter part of a newly allocated register window are identical with each other. Accordingly, the program can be rapidly executed.
In an RISC processor having a register window structure, the size of a register window is selected from among 2 to 32 by taking performance and hardware complexity into consideration. If the number of register windows is increased as described above, there is an advantage in that a program may be rapidly executed, but there is a disadvantage in that hardware complexity is increased because the number of registers forming a register window is increased. For this reason, the number of register windows is commonly 2 to 8.
If more procedures than register windows are called, a window overflow is generated, with the result that the transfer of a parameter using a window is made impossible. In this case, a processor has to generate a trap, and a window value has to be adjusted and register values have to be stored by a trap service routine. Consequently, a program cannot be rapidly executed as described above because a loss of cycles is increased.
U.S. Pat. No. 5,233,691 discloses a method of improving the ability to store a register window in a current procedure because a register window used in a procedure called in the past before an overflow is generated in a register file has already been stored at a point of time at which the overflow is generated by previously storing the registers of the past register window in stack memory using an external bus in an RISC processor having a register file. However, the method of the U.S. patent differs from a method of rapidly executing a program without a loss of cycles.
Furthermore, Korean Patent Laid-Open Publication No. 1999-0075766 discloses a method of reducing the mean time that it takes to process an interrupt by selecting, storing, and restoring only registers requiring storage and restoration when an interrupt is generated in an RISC type processor having a large number of registers. This Korean patent attempts to reduce the mean interrupt processing time by storing and restoring only values of V-registers that need to be stored in such a manner that only V-registers having changed values are selected when an interrupt is generated, the values of the selected V-registers are stored in memory, a value of a special register informing whether a write operation has been performed on the V-registers or not is stored in the memory, a relevant task is performed by calling a function, the stored value of the special register is restored, and only values of V-registers stored based on the restored value of the special register are selected and restored, without storing and restoring the values of all V-registers when an interrupt is generated in an RISC type processor. This method relates to a method of rapidly processing an interrupt by selectively storing and restoring registers using a known RISC processor, but differs from a method of rapidly executing a program without a loss of cycles.
The background of the present invention is disclosed in Korean Patent Laid-Open Publication No. 10-1999-0075766 (Oct. 15, 1999).